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DISCRETE SEMICONDUCTORS
DATA SHEET
BF909WR N-channel dual-gate MOS-FET
Product specification Supersedes data of 1995 Apr 25 File under Discrete Semiconductors, SC07 1997 Sep 05
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
FEATURES * Specially designed for use at 5 V supply voltage * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier up to 1 GHz * Superior cross-modulation performance during AGC. APPLICATIONS * VHF and UHF applications with 3 to 7 V supply voltage such as television tuners and professional communications equipment. DESCRIPTION Enhancement type field-effect transistor in a plastic microminiature SOT343R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj yfs Cig1-s Crs F drain current total power dissipation operating junction temperature forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure f = 1 MHz f = 800 MHz PARAMETER drain-source voltage CONDITIONS - - - - 36 - - - MIN. - - - - 43 3.6 30 2 TYP.
Marking code: ME.
handbook, halfpage
BF909WR
PINNING PIN 1 2 3 4 SYMBOL s, b d g2 g1 source drain gate 2 gate 1 DESCRIPTION
d
4
3
g2 g1
2 1
Top view
MAM192
s,b
Fig.1 Simplified outline (SOT343R) and symbol.
MAX. 7 40 280 150 50 4.3 50 2.8
UNIT V mA mW C mS pF fF dB
1997 Sep 05
2
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Device mounted on a printed-circuit board. PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation storage temperature range operating junction temperature up to Tamb = 50 C; see Fig.2; note 1 CONDITIONS - - - - - -65 - MIN. 7 40 10 10 280
BF909WR
MAX. V
UNIT mA mA mA mW C C
+150 +150
MLD150
handbook, halfpage
300
Ptot (mW) 200
100
0 0 50 100 150 200 Tamb ( oC)
Fig.2 Power derating curve.
1997 Sep 05
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-s Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-SS IG2-SS Note 1. RG1 connects gate 1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VDS = 5 V; VG2-S = 4 V; ID = 15 mA; unless otherwise specified. SYMBOL yfs Cig1-s Cig2-s Cos Crs F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 drain-source capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 800 MHz; GS = GSopt; BS = BSopt CONDITIONS pulsed; Tj = 25 C MIN. 36 - - - - - TYP. 43 3.6 2.3 2.3 30 2 PARAMETER gate 1-source breakdown voltage gate 2-source breakdown voltage forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current CONDITIONS VG2-S = VDS = 0; IG1-S = 10 mA VG1-S = VDS = 0; IG2-S = 10 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 20 A VG1-S = VDS = 5 V; ID = 20 A VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 5 V 6 6 0.5 0.5 0.3 0.3 12 - - MIN. PARAMETER thermal resistance from junction to ambient thermal resistance from junction to soldering point CONDITIONS note 1 Ts = 91 C; note 2
BF909WR
VALUE 350 210
UNIT K/W K/W
MAX. 15 15 1.5 1.5 1 1.2 20 50 50
UNIT V V V V V V mA nA nA
MAX. 50 4.3 3 3 50 2.8
UNIT mS pF pF pF fF dB
reverse transfer capacitance f = 1 MHz
1997 Sep 05
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF909WR
MLB937
MLB936
handbook, halfpage
110
handbook, halfpage
30
Vunw (dBV) 100
ID (mA)
V G2 S = 4 V 3 V
2.5 V
2V 20
1.5 V
90
10
1V
80 0 10 20 30 40 50 gain reduction (dB)
0 0 0.4 0.8 1.2 1.6 2.0 V G1 S (V)
VDS = 5 V; VGG = 5 V; fw = 50 MHz. funw = 60 MHz; Tamb = 25 C; RG1 = 120 k.
Fig.3
Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.17.
VDS = 5 V. Tj = 25 C.
Fig.4 Transfer characteristics; typical values.
MLB938
handbook, halfpage
30
V G1 S = 1.4 V
handbook, halfpage
200
MLB939
ID (mA) 20 1.3 V 1.2 V
I G1 (A) 150
V G2 S = 4 V
3.5 V
3V 1.1 V 1.0 V 0.9 V 50 100 2.5 V
10
2V
0 0 2 4 6 8 10 V DS (V)
0 0 1 2 V G1 S (V) 3
VDS = 5 V. VG2-S = 4 V. Tj = 25 C.
VDS = 5 V. Tj = 25 C.
Fig.6 Fig.5 Output characteristics; typical values.
Gate 1 current as a function of gate 1 voltage; typical values.
1997 Sep 05
5
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF909WR
MLB940
MLB941
handbook, halfpage
60
handbook, halfpage
25
y fs (mS) 40
V G2 S = 4 V 3.5 V 3V
ID (mA) 20
15 2.5 V 10 20 5
2V 0 0 10 20 I D (mA) 30 0 0 20 40 I G1 (A) 60
VDS = 5 V. Tj = 25 C.
VDS = 5 V. VG2-S = 4 V. Tj = 25 C.
Fig.7
Forward transfer admittance as a function of drain current; typical values.
Fig.8
Drain current as a function of gate 1 current; typical values.
handbook, halfpage
16
MLB942
MLB943
handbook, halfpage
30
ID (mA) 12
ID (mA) 20
R G1 = 47 k
68 k 82 k 100 k 120 k 150 k
8
180 k 220 k 10
4
0 0 2 4 V GG (V) 6
0 0 2 4 6 V GG = V DS (V) 8
VDS = 5 V; VG2-S = 4 V. RG1 = 120 k (connected to VGG); Tj = 25 C.
VG2-S = 4 V. RG1 connected to VGG; Tj = 25 C.
Fig.9
Drain current as a function of gate 1 supply voltage (= VGG); typical values; see Fig.17.
Fig.10 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values; see Fig.17.
1997 Sep 05
6
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF909WR
MLB944
handbook, halfpage
20
handbook, halfpage
40
MLB945
ID (mA) 16
V GG = 5 V 4.5 V 4V 3.5 V
I G1 (A) 30
V GG = 5 V 4.5 V 4V
12
3V 20
3.5 V 3V
8 10 4
0 0 2 4 V G2 S (V) 6
0 0 2 4 V G2 S (V) 6
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG).
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG).
Fig.11 Drain current as a function of gate 2 voltage; typical values; see Fig.17.
Fig.12 Gate 1 current as a function of gate 2 voltage; typical values; see Fig.17.
10 2 handbook, halfpage y is (mS) 10 b is
MLB946
10 3 y rs (S) 10 2
MLB947
10 3
rs (deg) rs
10 2
y rs 1 g is 10 10
10 1 10
102
f (MHz)
10 3
1 10
1 102 f (MHz) 10 3
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.13 Input admittance as a function of frequency; typical values.
Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values.
1997 Sep 05
7
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF909WR
10 2 y fs
MLB948
10 2
MLB949
handbook, halfpage
10
y fs (mS)
fs
(deg)
yos (mS) 1
bos
10
fs
10
gos 10 1
1 10
1 102 f (MHz) 10 3
10 2 10
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.15 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.16 Output admittance as a function of frequency; typical values.
VAGC R1 10 k
C1 4.7 nF C3 12 pF
C2 R GEN 50 VI R2 50 4.7 nF
R3 10 DUT R G1 C5 2.2 pF
L1
350 nH
C4 4.7 nF
RL 50
VGG
VDS
MLD151
Fig.17 Cross-modulation test set-up.
1997 Sep 05
8
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C s11 MAGNITUDE (ratio) 0.985 0.978 0.957 0.931 0.899 0.868 0.848 0.816 0.792 0.772 0.754 ANGLE (deg) -6.4 -12.6 -25.0 -36.5 -47.6 -57.4 -66.6 -74.6 -82.2 -89.3 -95.6 s21 MAGNITUDE (ratio) 4.064 3.997 3.886 3.682 3.484 3.260 3.053 2.829 2.652 2.470 2.328 ANGLE (deg) 172.3 164.9 150.8 137.3 123.8 111.7 101.0 90.3 79.9 69.5 59.5 s12 MAGNITUDE (ratio) 0.001 0.002 0.005 0.006 0.007 0.007 0.006 0.005 0.005 0.005 0.006 ANGLE (deg) 86.9 82.7 74.3 68.9 59.6 57.9 58.5 65.5 83.3 114.9 138.7
BF909WR
s22 MAGNITUDE (ratio) 0.985 0.982 0.973 0.960 0.947 0.936 0.927 0.919 0.913 0.910 0.909 ANGLE (deg) -3.2 -6.4 -12.6 -18.6 -24.2 -29.6 -34.8 -39.8 -44.6 -49.5 -54.6
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C f (MHz) 800 Fmin (dB) 2.00 opt (ratio) 0.603 (deg) 67.71 rn 0.581
1997 Sep 05
9
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
PACKAGE OUTLINE
BF909WR
handbook, full pagewidth
1.00 max 0.2 M A 0.2 M B 0.4 0.2 0.1 max 0.2 A
3
4
2.2 2.0
1.35 1.15
2
1
0.7 0.5 1.4 1.2 2.2 1.8 B
0.3 0.1 0.25 0.10
MSB367
Dimensions in mm.
Fig.18 SOT343R.
1997 Sep 05
10
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FET
DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values
BF909WR
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Sep 05
11
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
117067/00/02/pp12
Date of release: 1997 Sep 05
Document order number:
9397 750 02669

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